Embodiments of the present invention generally relate to integrated circuits and the processing for the manufacture of semiconductor devices. In particularly, embodiments of the invention provide a method and system for performing patterning processes for the manufacture of integrated circuit devices. More particularly, embodiments of the present method provide an image capturing and processing technique for identifying repeating pattern defects in a retical mask used for the manufacture of integrated circuits. But it would be recognized that the invention has a much broader range of applicability. As merely an example, the method and system can be applied to other devices such as micro electrical mechanical systems, display devices, and others.
Integrated circuits have evolved from a handful of interconnected devices fabricated on a single chip of silicon to millions of devices. Conventional integrated circuits provide performance and complexity far beyond what was originally imagined. In order to achieve improvements in complexity and circuit density (i.e., the number of devices capable of being packed onto a given chip area), the size of the smallest device feature, also known as the device “geometry”, has become smaller with each generation of integrated circuits.
Increasing circuit density has not only improved the complexity and performance of integrated circuits but has also provided lower cost parts to the consumer. An integrated circuit or chip fabrication facility can cost hundreds of millions, or even billions, of U.S. dollars. Each fabrication facility will have a certain throughput of wafers, and each wafer will have a certain number of integrated circuits on it. Therefore, by making the individual devices of an integrated circuit smaller, more devices may be fabricated on each wafer, thus increasing the output of the fabrication facility. Making devices smaller is very challenging, as each process used in integrated fabrication has a limit. That is to say, a given process typically only works down to a certain feature size, and then either the process or the device layout needs to be changed. Additionally, as devices require faster and faster designs, process limitations exist with certain conventional processes and materials.
An example of a process that has limitations based upon a given feature size is lithographic techniques for MOS transistor devices. As merely an example, lithography has been a major limitation as device sizes continue to become smaller. A major issue is repeating defects that occur in the manufacture of integrated circuits. These repeating defects are often difficult to determine and often cause high yield losses when they are undetected. These and other limitations associated with conventional lithography processes can be found throughout the present specification and more particularly below.
From the above, it is seen that an improved technique for processing semiconductor devices is desired.